/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** *****************************************************************************************************
 *  \file     Sent_Etimer_Register.h                                                                    *
 *  \brief    This file contains interface header for SENT_ETIMER MCAL driver                           *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2025/02/14     <td>1.0.0                                                                     *
 * </table>                                                                                             *
 *******************************************************************************************************/
#ifndef SENTETIMER_REGISTER_H
#define SENTETIMER_REGISTER_H

extern VAR(uint32, SENT_VAR) SENT_ETMR_BASE[TIMER_MODULE_NUMBER];

#define SENT_FIFO_OVR_STA_ADDR32(tmr)     (SENT_ETMR_BASE[tmr])
#define SENT_FIFO_OVR_STA_EN_ADDR32(tmr)  (SENT_ETMR_BASE[tmr] + (uint32)0x4U)
#define SENT_FIFO_OVR_STA_CHN_EN(cha)              (0x1CUL + (uint32)(cha))

#define SENT_INT_STA_ADDR32(tm)          (SENT_ETMR_BASE[tm])
#define SENT_INT_STA_EN_ADDR32(tm)       (SENT_ETMR_BASE[tm] + (uint32)0x4U)
#define SENT_INT_SIG_EN_ADDR32(tm)       (SENT_ETMR_BASE[tm] + (uint32)0x8U)

#define SENT_COR_ERR_INT_SIG_EN(tmr)      (SENT_ETMR_BASE[tmr] + (uint32)0x14U)
#define SENT_COR_ERR_NOT_FETCH_EN_BIT(cha)         (24UL + (uint32)(cha))

#define SENT_UNC_ERR_INT_SIG_EN(tmr)      (SENT_ETMR_BASE[tmr] + (uint32)0x20U)
#define SENT_UNC_ERR_NOT_FETCH_EN_BIT(cha)         (24UL + (uint32)(cha))

#define SENT_FIFO_ADDR32(tm, cha)        (SENT_ETMR_BASE[tm] + (uint32)0xC0U + ((uint32)cha*0x4u))

#define SENT_TIM_CLK_CONFIG(tm)          (SENT_ETMR_BASE[tm] + (uint32)0xA0U)
#define SENT_BM_TIM_CLK_CONFIG_CLK_CHANGE_UPD (0x01UL << 31U)
#define SENT_FM_TIM_CLK_CONFIG_SRC_CLK_SEL (0x3UL << 16U)
#define SENT_FV_TIM_CLK_CONFIG_SRC_CLK_SEL(v) \
    (((v) << 16U) & SENT_FM_TIM_CLK_CONFIG_SRC_CLK_SEL)
#define SENT_FM_TIM_CLK_CONFIG_DIV_NUM (0xffffU << 0U)
#define SENT_FV_TIM_CLK_CONFIG_DIV_NUM(v) \
    (((v) << 0U) & SENT_FM_TIM_CLK_CONFIG_DIV_NUM)

#define SENT_RST_CHANNEL(tm)             (SENT_ETMR_BASE[tm] + (uint32)0xA8U)

#define SENT_FIFO_STA(tm)                (SENT_ETMR_BASE[tm] + (uint32)0xD0U)

#define SENT_LOCAL_CNT_CFG(tm,cha)       (SENT_ETMR_BASE[tm] + (uint32)0x148U + ((uint32)(cha)*0x20U))

#define SENT_CNT_CFG_START_BY_FIRST_CPT_START_BIT   (uint32)25U
#define SENT_CNT_CFG_CPT1_CLR_EN_START_BIT          (uint32)24U
#define SENT_CNT_CFG_CPT0_CLR_EN_START_BIT          (uint32)23U
#define SENT_CNT_CFG_INIT_UPD_START_BIT             (uint32)16U
#define SENT_CNT_CFG_OVF_UPD_START_BIT              (uint32)17U


#define ETMR_BM_LCNT_CFG_OVF_RST_DIS (0x01U << 28U)
#define ETMR_BM_LCNT_CFG_DELTA_TIME_EN (0x01U << 27U)
#define ETMR_BM_LCNT_CFG_SIG_EN (0x01U << 26U)
#define ETMR_BM_LCNT_CFG_START_BY_FIRST_CPT (0x01U << 25U)
#define ETMR_BM_LCNT_CFG_CPT1_CLR_EN (0x01U << 24U)
#define ETMR_BM_LCNT_CFG_CPT0_CLR_EN (0x01U << 23U)
#define ETMR_FM_LCNT_CFG_SIG_TRIG_SEL (0x3U << 21U)
#define ETMR_FV_LCNT_CFG_SIG_TRIG_SEL(v) \
    (((v) << 21U) & ETMR_FM_LCNT_CFG_SIG_TRIG_SEL)
#define ETMR_BM_LCNT_CFG_NO_STOP_OVF_MODE (0x01U << 20U)
#define ETMR_BM_LCNT_CFG_NO_STOP_MODE (0x01U << 19U)
#define ETMR_BM_LCNT_CFG_CON_MODE (0x01U << 18U)
#define ETMR_BM_LCNT_CFG_OVF_UPD (0x01U << 17U)
#define ETMR_BM_LCNT_CFG_INIT_UPD (0x01U << 16U)
#define ETMR_FM_LCNT_CFG_INTERVAL (0xffU << 8U)
#define ETMR_FV_LCNT_CFG_INTERVAL(v) \
    (((v) << 8U) & ETMR_FM_LCNT_CFG_INTERVAL)
#define ETMR_BM_LCNT_CFG_CE_EN (0x01U << 7U)
#define ETMR_FM_LCNT_CFG_CLR_TRIG_SEL (0x3U << 5U)
#define ETMR_FV_LCNT_CFG_CLR_TRIG_SEL(v) \
    (((v) << 5U) & ETMR_FM_LCNT_CFG_CLR_TRIG_SEL)
#define ETMR_FM_LCNT_CFG_SET_UPD_SEL (0x3U << 3U)
#define ETMR_FV_LCNT_CFG_SET_UPD_SEL(v) \
    (((v) << 3U) & ETMR_FM_LCNT_CFG_SET_UPD_SEL)
#define ETMR_FM_LCNT_CFG_SET_TRIG_SEL (0x3U << 1U)
#define ETMR_FV_LCNT_CFG_SET_TRIG_SEL(v) \
    (((v) << 1U) & ETMR_FM_LCNT_CFG_SET_TRIG_SEL)
#define ETMR_BM_LCNT_CFG_FRC_RLD (0x01U << 0U)


#define SENT_LOCAL_CNT(tm,cha)           (SENT_ETMR_BASE[tm] + (uint32)0x150U + (cha)*0x20U)

#define SENT_LOCAL_CNT_EN(tm, cha)       (SENT_ETMR_BASE[tm] + (uint32)0x14Cu + ((uint32)(cha)*0x20u))
#define SENT_LOCAL_CNT_OVF_VAL(tm, cha)  (SENT_ETMR_BASE[tm] + (uint32)0x144u + ((uint32)(cha)*0x20u))

#define SENT_CPT_CONFIG(tm, cha)         (SENT_ETMR_BASE[tm] + (uint32)0x200u + ((uint32)cha*0x4u))
#define SENT_CPT_CONFIG_CPT0_TRIG_MODE_START_BIT                   (uint32)(2u)
#define SENT_CPT_CONFIG_CPT1_TRIG_MODE_START_BIT                   (uint32)(4u)
#define SENT_CPT_CONFIG_CNT_SEL_START_BIT                          (uint32)(6u)

#define SENT_CHN_DMA_CTRL(tm)            (SENT_ETMR_BASE[tm] + (uint32)0xB0U)
#define SENT_BM_CHN_DMA_CTRL_CHN_16BIT_MODE(cha) (0x01U << (16U + (cha)))
#define SENT_BM_CHN_DMA_CTRL_CHN_SIG_MASK(cha) (0x01U << (12U + (cha)))
#define SENT_FM_CHN_DMA_CTRL_CHN_SEL(cha) ((uint32)0x3U << (4U + (uint32)(cha)*0x2U))
#define SENT_FV_CHN_DMA_CTRL_CHN_SEL(v, cha) \
                    (((uint32)(v) << (4U + ((uint32)(cha)*0x2U))) & SENT_FM_CHN_DMA_CTRL_CHN_SEL(cha))
#define SENT_BM_CHN_DMA_CTRL_CHN_EN(cha) ((uint32)0x01U << (uint32)(cha))


#define SENT_CHN_DMA_WML(tm)          (SENT_ETMR_BASE[tm] + (uint32)0xB4U)
#define SENT_FM_DMA_WML_CHN(cha) ((uint32)0xfU << ((uint32)(cha)*0x8U))
#define SENT_FV_DMA_WML_CHN(v, cha) (((uint32)(v) << ((uint32)(cha)*0x8U)) & SENT_FM_DMA_WML_CHN(cha))

#define SENT_CPT_X0_FLT(tm, cha)         (SENT_ETMR_BASE[tm] + 0x400u + ((uint32)cha*0x4u))
#define SENT_CPT_FLT_EN             ((uint32)0x1U << (uint32)0U)
#define SENT_CPT_FLT_DISEN          ((uint32)0x0U << (uint32)0U)
#define SENT_CPT_FLT_POSEDGE_SEL    ((uint32)0x0U << (uint32)1U)
#define SENT_CPT_FLT_NEGEDGE_SEL    ((uint32)0x1U << (uint32)1U)
#define SENT_CPT_FLT_BOTHEDGE_SEL   ((uint32)0x2U << (uint32)1U)
#define SENT_CPT_FLT_POS_BAND_WID(v) (((uint32)v & 0xFU) << (uint32)4U)
#define SENT_CPT_FLT_NEG_BAND_WID(v) (((uint32)v & 0xFU) << (uint32)8U)
#define SENT_CPT_FLT_SMPL_INTVAL(v)  (((uint32)v & 0xFFU) << (uint32)12U)

#define SENT_CPT_CTRL(tm)                (SENT_ETMR_BASE[tm] + (uint32)0x210U)
#define SENT_CPT_CTRL_CPT_CONFIG_SET_START_BIT(cha)     (uint32)(4U + (uint32)(cha))
#define SENT_CPT_CTRL_CPT_EN_START_BIT(cha)      (uint32)(cha)

#endif /* SENTETIMER_REGISTER_H */
/* End of file */
